Recently, in the wiring design work on a multilayer board having plural layers, it is normal that the requested signal speed is increased and design constraints are designated. The design constraints may include designation of the length of the wiring path, or instruction to make the lengths of the respective wiring paths included in a group having plural wiring paths, such as bus, identical in order to match the timings of the signals flowing in signal lines between components.
For example, as illustrated in FIG. 1, when the signals have to reach at the same timing from drivers 1000 that are transmission sources of the signals to receivers 1100 that are destinations of the signals, an equal line-length condition that the lengths of all wiring paths are equal is set.
In addition, as illustrated in FIG. 2A (top view) and FIG. 2B (cross section), in case of the multilayer board, the wiring can be made by using a via 1001 from a signal terminal 1004 in a first layer L1 to a signal terminal 1003 (e.g. a terminal of a semiconductor chip IC1) in a second layer L2. However, because the respective signals delay in wired lines 1002 passing across plural layers through the via 1001, the wiring on a single layer without using the via is requested as illustrated in FIG. 2C.
However, when a lot of signals from start terminals A to end terminals B are wired on a single layer as illustrated in FIG. 3A, the wiring area becomes board due to the bypass of the wired lines as illustrated in FIG. 3B, and the difference of the length among the signal lines becomes large.
As schematically illustrated in FIG. 4A, when the wiring area 1600 is made small for the high-density packaging, the longest length of the lines to be wired from the drivers to the receivers is shortened. However, when reducing the wiring area is emphasized, a case may occur where the variation arises in the lengths of the signal lines, and it is difficult to carry out adjustment for complying with the aforementioned equal line-length condition.
On the other hand, as schematically illustrated in FIG. 4B, when the equal line-length condition is emphasized and the wiring is carried out so as to reduce the difference of the lengths of the lines, a case may occur where the longest length of the line among the lengths of the lines to be wired from the drivers to the receivers becomes long, the wiring area 1700 becomes large and the high density wiring becomes difficult, accordingly.
Therefore, it is desired that, when the signal lines to be wired are grouped to the plural layers, such problems do not occur in each layer.
However, it is often difficult to appropriately group the signal lines to be wired to plural layers, manually. More specially, an inefficient job is carried out that the grouping and subsequent tasks are redone, when it is known later that the wiring cannot be made so as to satisfy the requirements.
In addition, an automatic design technique exists in which a virtual wiring area of the signal lines is calculated, the number of signals in an area, which overlaps with another area for other signal lines, is adjusted, and some signal lines are moved to another layer. However, this conventional technique assumes other signal lines exist, and the problem on the difference of the lengths among the signal lines is not considered.
Furthermore, a method also exists, in which the signal lines are grouped by evaluating the disposition of the components and the density of the wires to search for the optimum paths by disposing the respective grouped signal lines so as to be as close as possible. However, even by this technique, there is a case where the problem concerning the lengths of the lines cannot be solved, because no constraints are considered in the grouping. Moreover, the efficiency is poor, because a procedure including reconsidering the rough paths of the grouped signal lines and evaluating the rough paths is repeated. Moreover, there is no consideration also for the efficiency improvement for the wiring area.
Furthermore, a technique exists in which intervals of plural signal lines are estimated, the plural signal lines are wired by the bundle, and when the arrangement of the output terminals is the same as that of the input terminals, the wiring is made on the same layer of the printed circuit board, and when the arrangement of the output terminals is different from that of the input terminals, the signal lines are assigned to two layers by providing a switching area in an arbitrary bending area. However, the assigning the signal lines to two layers means connecting the signal lines through the via, so the constraint is not satisfied with the aforementioned single-layer wiring.
When plural signal lines to be wired are grouped in order to carry out the single-layer wiring in plural layers, the matters to be considered are as follows: Namely, those are easiness of adjusting the lengths of the lines, which means making it easy to satisfy the equal line-length condition, and easiness of the wiring, which means making it easy to carry out the wiring without concentrating the signal lines and/or the signal terminals to reduce the wiring area. Moreover, there is a problem concerning which of them has priority when both of them are to be considered. It is impossible for the conventional arts to group the plural signal lines so as to cope with such problems.